diff --git a/ac108.c b/ac108.c
index 635e316..0aa7fdb 100644
--- a/ac108.c
+++ b/ac108.c
@@ -22,7 +22,6 @@
 #include <sound/soc.h>
 #include <sound/initval.h>
 #include <sound/tlv.h>
-#include <sound/wm8960.h>
 
 #include "ac108.h"
 
@@ -755,6 +754,34 @@ static int ac108_configure_clocking(struct ac108_priv *ac108, unsigned int rate)
 	return 0;
 }
 
+/*
+ * support no more than 16 slots.
+ */
+static int ac108_multi_chips_slots(struct ac108_priv *ac, int slots) {
+	int i;
+
+	/* codec0 enable slots 1,2,3,4
+	 * codec1 enable slots 5,6,7,8 etc
+	 */
+	for (i = 0; i < ac->codec_index; i++) {
+		unsigned vec;
+
+		/* 0x38-0x3A I2S_TX1_CTRLx */
+		vec = 0xFUL << (i << 2);
+		ac108_write(I2S_TX1_CTRL1, slots - 1, ac->i2c[i]);
+		ac108_write(I2S_TX1_CTRL2, (vec >> 0) & 0xFF, ac->i2c[i]);
+		ac108_write(I2S_TX1_CTRL3, (vec >> 8) & 0xFF, ac->i2c[i]);
+
+		/* 0x3C-0x3F I2S_TX1_CHMP_CTRLx */
+		vec = (0x0 << 0 | 0x1 << 2 | 0x2 << 4 | 0x3 << 6) << (i << 3);
+		ac108_write(I2S_TX1_CHMP_CTRL1, (vec >>  0) & 0xFF, ac->i2c[i]);
+		ac108_write(I2S_TX1_CHMP_CTRL2, (vec >>  8) & 0xFF, ac->i2c[i]);
+		ac108_write(I2S_TX1_CHMP_CTRL3, (vec >> 16) & 0xFF, ac->i2c[i]);
+		ac108_write(I2S_TX1_CHMP_CTRL4, (vec >> 24) & 0xFF, ac->i2c[i]);
+	}
+	return 0;
+}
+
 static int ac108_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) {
 	unsigned int i, channels, sample_resolution, rate;
 	struct snd_soc_codec *codec = dai->codec;
@@ -867,8 +894,12 @@ static int ac108_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_h
 			break;
 		}
 	}
-
 	ac108_multi_chips_update_bits(I2S_BCLK_CTRL,  0x0F << BCLKDIV, i << BCLKDIV, ac108);
+
+	/*
+	 * slots allocation for each chip
+	 */
+	ac108_multi_chips_slots(ac108, channels);
 	return 0;
 }
 
@@ -910,6 +941,8 @@ static int ac108_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) {
 
 	unsigned char tx_offset, lrck_polarity, brck_polarity;
 	struct ac108_priv *ac108 = dev_get_drvdata(dai->dev);
+	int i;
+
 	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 	case SND_SOC_DAIFMT_CBM_CFM:    /*AC108 Master*/
 		dev_dbg(dai->dev, "AC108 set to work as Master\n");
@@ -919,8 +952,9 @@ static int ac108_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) {
 		ac108_multi_chips_update_bits(I2S_CTRL, 0x03 << LRCK_IOEN | 0x03 << SDO1_EN | 0x1 << TXEN | 0x1 << GEN,
 							0x03 << LRCK_IOEN | 0x03 << SDO1_EN | 0x1 << TXEN | 0x1 << GEN, ac108);
 		/* multi_chips: only one chip set as Master, and the others also need to set as Slave */
-		if (ac108->codec_index > 1) ac108_update_bits(I2S_CTRL, 0x3 << LRCK_IOEN, 0x0 << LRCK_IOEN, ac108->i2c[1]);
-
+		for (i = 1; i < ac108->codec_index; i++) {
+			ac108_update_bits(I2S_CTRL, 0x3 << LRCK_IOEN, 0x0 << LRCK_IOEN, ac108->i2c[i]);
+		}
 		break;
 	case SND_SOC_DAIFMT_CBS_CFS:    /*AC108 Slave*/
 		dev_dbg(dai->dev, "AC108 set to work as Slave\n");
@@ -1183,7 +1217,7 @@ static const struct snd_soc_codec_driver ac108_soc_codec_driver = {
 
 static ssize_t ac108_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) {
 	int val = 0, flag = 0;
-	u8 i = 0, reg, num, value_w, value_r;
+	u8 i = 0, reg, num, value_w, value_r[4];
 
 	val = simple_strtol(buf, NULL, 16);
 	flag = (val >> 16) & 0xF;
@@ -1199,12 +1233,23 @@ static ssize_t ac108_store(struct device *dev, struct device_attribute *attr, co
 		printk("\nRead: start REG:0x%02x,count:0x%02x\n", reg, num);
 
 		do {
-			value_r = 0;
-			ac108_multi_chips_read(reg, &value_r, ac108);
-			printk("REG[0x%02x]: 0x%02x;  ", reg, value_r);
+			int k;
+
+			memset(value_r, 0, sizeof value_r);
+
+			for (k = 0; k < ac108->codec_index; k++) {
+				ac108_read(reg, &value_r[k], ac108->i2c[k]);
+			}
+			if (ac108->codec_index >= 2) {
+				printk("REG[0x%02x]: 0x%02x 0x%02x", reg, value_r[0], value_r[1]);
+			} else {
+				printk("REG[0x%02x]: 0x%02x", reg, value_r[0]);
+			}
 			reg++;
-			i++;
-			if ((i == num) || (i % 4 == 0))	printk("\n");
+
+			if ((++i == num) || (i % 4 == 0)) {
+				printk("\n");
+			}
 		} while (i < num);
 	}
 
@@ -1261,6 +1306,10 @@ static int ac108_i2c_probe(struct i2c_client *i2c,
 	ac108->data_protocol = val;
 
 
+	/*Writing this register 0x12 resets all register to their default state.*/
+	ac108_write(CHIP_RST, CHIP_RST_VAL, i2c);
+	msleep(1);
+
 	pr_err(" i2c_id number :%d\n", (int)(i2c_id->driver_data));
 	pr_err(" ac108  codec_index :%d\n", ac108->codec_index);
 	pr_err(" ac108  I2S data protocol type :%d\n", ac108->data_protocol);
@@ -1275,9 +1324,6 @@ static int ac108_i2c_probe(struct i2c_client *i2c,
 
 	ac108->codec_index++;
 
-	/*Writing this register 0x12 resets all register to their default state.*/
-	ac108_write(CHIP_RST, CHIP_RST_VAL, i2c);
-
 	ret = sysfs_create_group(&i2c->dev.kobj, &ac108_debug_attr_group);
 	if (ret) {
 		pr_err("failed to create attr group\n");
diff --git a/ac108_8mic.state b/ac108_8mic.state
new file mode 100644
index 0000000..e9411fe
--- /dev/null
+++ b/ac108_8mic.state
@@ -0,0 +1,953 @@
+state.ALSA {
+	control.1 {
+		iface MIXER
+		name 'PCM Playback Volume'
+		value 400
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '-10239 - 400'
+			dbmin -9999999
+			dbmax 400
+			dbvalue.0 400
+		}
+	}
+	control.2 {
+		iface MIXER
+		name 'PCM Playback Switch'
+		value true
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.3 {
+		iface MIXER
+		name 'PCM Playback Route'
+		value 0
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 2'
+		}
+	}
+	control.4 {
+		iface PCM
+		name 'IEC958 Playback Default'
+		value '0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000'
+		comment {
+			access 'read write'
+			type IEC958
+			count 1
+		}
+	}
+	control.5 {
+		iface PCM
+		name 'IEC958 Playback Con Mask'
+		value '0200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000'
+		comment {
+			access read
+			type IEC958
+			count 1
+		}
+	}
+	control.6 {
+		iface PCM
+		name 'IEC958 Playback PCM Stream'
+		value '0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000'
+		comment {
+			access 'read write inactive'
+			type IEC958
+			count 1
+		}
+	}
+}
+state.seeed8micvoicec {
+	control.1 {
+		iface MIXER
+		name 'OUT1 Mute'
+		value false
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.2 {
+		iface MIXER
+		name 'OUT2 Mute'
+		value true
+		comment {
+			access 'read write'
+			type BOOLEAN
+			count 1
+		}
+	}
+	control.3 {
+		iface MIXER
+		name 'TX1 Channel1~8 enable'
+		value '1-4 channels '
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 'disable all'
+			item.1 '1-1 channels '
+			item.2 '1-2 channels '
+			item.3 '1-3 channels '
+			item.4 '1-4 channels '
+			item.5 '1-5 channels '
+			item.6 '1-6 channels '
+			item.7 '1-7 channels '
+			item.8 '1-8 channels '
+		}
+	}
+	control.4 {
+		iface MIXER
+		name 'TX1 Channel9~16 enable'
+		value 'disable all'
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 'disable all'
+			item.1 '8-9 channels '
+			item.2 '8-10 channels '
+			item.3 '8-11 channels '
+			item.4 '8-12 channels '
+			item.5 '8-13 channels '
+			item.6 '8-14 channels '
+			item.7 '8-15 channels '
+			item.8 '8-16 channels '
+		}
+	}
+	control.5 {
+		iface MIXER
+		name 'TX2 Channel1~8 enable'
+		value 'disable all'
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 'disable all'
+			item.1 '1-1 channels '
+			item.2 '1-2 channels '
+			item.3 '1-3 channels '
+			item.4 '1-4 channels '
+			item.5 '1-5 channels '
+			item.6 '1-6 channels '
+			item.7 '1-7 channels '
+			item.8 '1-8 channels '
+		}
+	}
+	control.6 {
+		iface MIXER
+		name 'TX2 Channel9~16 enable'
+		value 'disable all'
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 'disable all'
+			item.1 '8-9 channels '
+			item.2 '8-10 channels '
+			item.3 '8-11 channels '
+			item.4 '8-12 channels '
+			item.5 '8-13 channels '
+			item.6 '8-14 channels '
+			item.7 '8-15 channels '
+			item.8 '8-16 channels '
+		}
+	}
+	control.7 {
+		iface MIXER
+		name 'CH1 digital volume'
+		value 181
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 255'
+			dbmin -11925
+			dbmax 7200
+			dbvalue.0 1650
+		}
+	}
+	control.8 {
+		iface MIXER
+		name 'CH2 digital volume'
+		value 181
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 255'
+			dbmin -11925
+			dbmax 7200
+			dbvalue.0 1650
+		}
+	}
+	control.9 {
+		iface MIXER
+		name 'CH3 digital volume'
+		value 181
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 255'
+			dbmin -11925
+			dbmax 7200
+			dbvalue.0 1650
+		}
+	}
+	control.10 {
+		iface MIXER
+		name 'CH4 digital volume'
+		value 181
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 255'
+			dbmin -11925
+			dbmax 7200
+			dbvalue.0 1650
+		}
+	}
+	control.11 {
+		iface MIXER
+		name 'ADC1 PGA gain'
+		value 27
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 31'
+			dbmin 0
+			dbmax 3100
+			dbvalue.0 2700
+		}
+	}
+	control.12 {
+		iface MIXER
+		name 'ADC2 PGA gain'
+		value 27
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 31'
+			dbmin 0
+			dbmax 3100
+			dbvalue.0 2700
+		}
+	}
+	control.13 {
+		iface MIXER
+		name 'ADC3 PGA gain'
+		value 27
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 31'
+			dbmin 0
+			dbmax 3100
+			dbvalue.0 2700
+		}
+	}
+	control.14 {
+		iface MIXER
+		name 'ADC4 PGA gain'
+		value 27
+		comment {
+			access 'read write'
+			type INTEGER
+			count 1
+			range '0 - 31'
+			dbmin 0
+			dbmax 3100
+			dbvalue.0 2700
+		}
+	}
+	control.15 {
+		iface MIXER
+		name 'Tx1 Channels'
+		value '4 channels '
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 '1 channels '
+			item.1 '2 channels '
+			item.2 '3 channels '
+			item.3 '4 channels '
+			item.4 '5 channels '
+			item.5 '6 channels '
+			item.6 '7 channels '
+			item.7 '8 channels '
+			item.8 '9 channels '
+			item.9 '10 channels '
+			item.10 '11 channels '
+			item.11 '12 channels '
+			item.12 '13 channels '
+			item.13 '14 channels '
+			item.14 '15 channels '
+			item.15 '16 channels '
+		}
+	}
+	control.16 {
+		iface MIXER
+		name 'Tx2 Channels'
+		value '1 channels '
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 '1 channels '
+			item.1 '2 channels '
+			item.2 '3 channels '
+			item.3 '4 channels '
+			item.4 '5 channels '
+			item.5 '6 channels '
+			item.6 '7 channels '
+			item.7 '8 channels '
+			item.8 '9 channels '
+			item.9 '10 channels '
+			item.10 '11 channels '
+			item.11 '12 channels '
+			item.12 '13 channels '
+			item.13 '14 channels '
+			item.14 '15 channels '
+			item.15 '16 channels '
+		}
+	}
+	control.17 {
+		iface MIXER
+		name 'Tx1 Channels 1 MAP'
+		value '1st adc sample'
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 '1st adc sample'
+			item.1 '2st adc sample'
+			item.2 '3st adc sample'
+			item.3 '4st adc sample'
+		}
+	}
+	control.18 {
+		iface MIXER
+		name 'Tx1 Channels 2 MAP'
+		value '2st adc sample'
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 '1st adc sample'
+			item.1 '2st adc sample'
+			item.2 '3st adc sample'
+			item.3 '4st adc sample'
+		}
+	}
+	control.19 {
+		iface MIXER
+		name 'Tx1 Channels 3 MAP'
+		value '3st adc sample'
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 '1st adc sample'
+			item.1 '2st adc sample'
+			item.2 '3st adc sample'
+			item.3 '4st adc sample'
+		}
+	}
+	control.20 {
+		iface MIXER
+		name 'Tx1 Channels 4 MAP'
+		value '4st adc sample'
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 '1st adc sample'
+			item.1 '2st adc sample'
+			item.2 '3st adc sample'
+			item.3 '4st adc sample'
+		}
+	}
+	control.21 {
+		iface MIXER
+		name 'Tx1 Channels 5 MAP'
+		value '1st adc sample'
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 '1st adc sample'
+			item.1 '2st adc sample'
+			item.2 '3st adc sample'
+			item.3 '4st adc sample'
+		}
+	}
+	control.22 {
+		iface MIXER
+		name 'Tx1 Channels 6 MAP'
+		value '1st adc sample'
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 '1st adc sample'
+			item.1 '2st adc sample'
+			item.2 '3st adc sample'
+			item.3 '4st adc sample'
+		}
+	}
+	control.23 {
+		iface MIXER
+		name 'Tx1 Channels 7 MAP'
+		value '1st adc sample'
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 '1st adc sample'
+			item.1 '2st adc sample'
+			item.2 '3st adc sample'
+			item.3 '4st adc sample'
+		}
+	}
+	control.24 {
+		iface MIXER
+		name 'Tx1 Channels 8 MAP'
+		value '1st adc sample'
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 '1st adc sample'
+			item.1 '2st adc sample'
+			item.2 '3st adc sample'
+			item.3 '4st adc sample'
+		}
+	}
+	control.25 {
+		iface MIXER
+		name 'Tx1 Channels 9 MAP'
+		value '1st adc sample'
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 '1st adc sample'
+			item.1 '2st adc sample'
+			item.2 '3st adc sample'
+			item.3 '4st adc sample'
+		}
+	}
+	control.26 {
+		iface MIXER
+		name 'Tx1 Channels 10 MAP'
+		value '1st adc sample'
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 '1st adc sample'
+			item.1 '2st adc sample'
+			item.2 '3st adc sample'
+			item.3 '4st adc sample'
+		}
+	}
+	control.27 {
+		iface MIXER
+		name 'Tx1 Channels 11 MAP'
+		value '1st adc sample'
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 '1st adc sample'
+			item.1 '2st adc sample'
+			item.2 '3st adc sample'
+			item.3 '4st adc sample'
+		}
+	}
+	control.28 {
+		iface MIXER
+		name 'Tx1 Channels 12 MAP'
+		value '1st adc sample'
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 '1st adc sample'
+			item.1 '2st adc sample'
+			item.2 '3st adc sample'
+			item.3 '4st adc sample'
+		}
+	}
+	control.29 {
+		iface MIXER
+		name 'Tx1 Channels 13 MAP'
+		value '1st adc sample'
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 '1st adc sample'
+			item.1 '2st adc sample'
+			item.2 '3st adc sample'
+			item.3 '4st adc sample'
+		}
+	}
+	control.30 {
+		iface MIXER
+		name 'Tx1 Channels 14 MAP'
+		value '1st adc sample'
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 '1st adc sample'
+			item.1 '2st adc sample'
+			item.2 '3st adc sample'
+			item.3 '4st adc sample'
+		}
+	}
+	control.31 {
+		iface MIXER
+		name 'Tx1 Channels 15 MAP'
+		value '1st adc sample'
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 '1st adc sample'
+			item.1 '2st adc sample'
+			item.2 '3st adc sample'
+			item.3 '4st adc sample'
+		}
+	}
+	control.32 {
+		iface MIXER
+		name 'Tx1 Channels 16 MAP'
+		value '1st adc sample'
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 '1st adc sample'
+			item.1 '2st adc sample'
+			item.2 '3st adc sample'
+			item.3 '4st adc sample'
+		}
+	}
+	control.33 {
+		iface MIXER
+		name 'Tx2 Channels 1 MAP'
+		value '1st adc sample'
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 '1st adc sample'
+			item.1 '2st adc sample'
+			item.2 '3st adc sample'
+			item.3 '4st adc sample'
+		}
+	}
+	control.34 {
+		iface MIXER
+		name 'Tx2 Channels 2 MAP'
+		value '1st adc sample'
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 '1st adc sample'
+			item.1 '2st adc sample'
+			item.2 '3st adc sample'
+			item.3 '4st adc sample'
+		}
+	}
+	control.35 {
+		iface MIXER
+		name 'Tx2 Channels 3 MAP'
+		value '1st adc sample'
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 '1st adc sample'
+			item.1 '2st adc sample'
+			item.2 '3st adc sample'
+			item.3 '4st adc sample'
+		}
+	}
+	control.36 {
+		iface MIXER
+		name 'Tx2 Channels 4 MAP'
+		value '1st adc sample'
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 '1st adc sample'
+			item.1 '2st adc sample'
+			item.2 '3st adc sample'
+			item.3 '4st adc sample'
+		}
+	}
+	control.37 {
+		iface MIXER
+		name 'Tx2 Channels 5 MAP'
+		value '1st adc sample'
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 '1st adc sample'
+			item.1 '2st adc sample'
+			item.2 '3st adc sample'
+			item.3 '4st adc sample'
+		}
+	}
+	control.38 {
+		iface MIXER
+		name 'Tx2 Channels 6 MAP'
+		value '1st adc sample'
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 '1st adc sample'
+			item.1 '2st adc sample'
+			item.2 '3st adc sample'
+			item.3 '4st adc sample'
+		}
+	}
+	control.39 {
+		iface MIXER
+		name 'Tx2 Channels 7 MAP'
+		value '1st adc sample'
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 '1st adc sample'
+			item.1 '2st adc sample'
+			item.2 '3st adc sample'
+			item.3 '4st adc sample'
+		}
+	}
+	control.40 {
+		iface MIXER
+		name 'Tx2 Channels 8 MAP'
+		value '1st adc sample'
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 '1st adc sample'
+			item.1 '2st adc sample'
+			item.2 '3st adc sample'
+			item.3 '4st adc sample'
+		}
+	}
+	control.41 {
+		iface MIXER
+		name 'Tx2 Channels 9 MAP'
+		value '1st adc sample'
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 '1st adc sample'
+			item.1 '2st adc sample'
+			item.2 '3st adc sample'
+			item.3 '4st adc sample'
+		}
+	}
+	control.42 {
+		iface MIXER
+		name 'Tx2 Channels 10 MAP'
+		value '1st adc sample'
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 '1st adc sample'
+			item.1 '2st adc sample'
+			item.2 '3st adc sample'
+			item.3 '4st adc sample'
+		}
+	}
+	control.43 {
+		iface MIXER
+		name 'Tx2 Channels 11 MAP'
+		value '1st adc sample'
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 '1st adc sample'
+			item.1 '2st adc sample'
+			item.2 '3st adc sample'
+			item.3 '4st adc sample'
+		}
+	}
+	control.44 {
+		iface MIXER
+		name 'Tx2 Channels 12 MAP'
+		value '1st adc sample'
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 '1st adc sample'
+			item.1 '2st adc sample'
+			item.2 '3st adc sample'
+			item.3 '4st adc sample'
+		}
+	}
+	control.45 {
+		iface MIXER
+		name 'Tx2 Channels 13 MAP'
+		value '1st adc sample'
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 '1st adc sample'
+			item.1 '2st adc sample'
+			item.2 '3st adc sample'
+			item.3 '4st adc sample'
+		}
+	}
+	control.46 {
+		iface MIXER
+		name 'Tx2 Channels 14 MAP'
+		value '1st adc sample'
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 '1st adc sample'
+			item.1 '2st adc sample'
+			item.2 '3st adc sample'
+			item.3 '4st adc sample'
+		}
+	}
+	control.47 {
+		iface MIXER
+		name 'Tx2 Channels 15 MAP'
+		value '1st adc sample'
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 '1st adc sample'
+			item.1 '2st adc sample'
+			item.2 '3st adc sample'
+			item.3 '4st adc sample'
+		}
+	}
+	control.48 {
+		iface MIXER
+		name 'Tx2 Channels 16 MAP'
+		value '1st adc sample'
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 '1st adc sample'
+			item.1 '2st adc sample'
+			item.2 '3st adc sample'
+			item.3 '4st adc sample'
+		}
+	}
+	control.49 {
+		iface MIXER
+		name 'ADC4 Source'
+		value 'Analog ADC4'
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 'Analog ADC1'
+			item.1 'Analog ADC2'
+			item.2 'Analog ADC3'
+			item.3 'Analog ADC4'
+		}
+	}
+	control.50 {
+		iface MIXER
+		name 'ADC3 Source'
+		value 'Analog ADC3'
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 'Analog ADC1'
+			item.1 'Analog ADC2'
+			item.2 'Analog ADC3'
+			item.3 'Analog ADC4'
+		}
+	}
+	control.51 {
+		iface MIXER
+		name 'ADC2 Source'
+		value 'Analog ADC2'
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 'Analog ADC1'
+			item.1 'Analog ADC2'
+			item.2 'Analog ADC3'
+			item.3 'Analog ADC4'
+		}
+	}
+	control.52 {
+		iface MIXER
+		name 'ADC1 Source'
+		value 'Analog ADC1'
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 'Analog ADC1'
+			item.1 'Analog ADC2'
+			item.2 'Analog ADC3'
+			item.3 'Analog ADC4'
+		}
+	}
+	control.53 {
+		iface MIXER
+		name 'ADC1 Digital Mixer gc'
+		value 'disable all'
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 'disable all'
+			item.1 'ADC1 data'
+			item.2 'ADC2 data'
+			item.3 'ADC3 data'
+			item.4 'ADC4 data'
+		}
+	}
+	control.54 {
+		iface MIXER
+		name 'ADC1 Digital Mixer src'
+		value 'ADC1 data'
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 'disable all'
+			item.1 'ADC1 data'
+			item.2 'ADC2 data'
+			item.3 'ADC3 data'
+			item.4 'ADC4 data'
+		}
+	}
+	control.55 {
+		iface MIXER
+		name 'ADC2 Digital Mixer gc'
+		value 'disable all'
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 'disable all'
+			item.1 'ADC1 data'
+			item.2 'ADC2 data'
+			item.3 'ADC3 data'
+			item.4 'ADC4 data'
+		}
+	}
+	control.56 {
+		iface MIXER
+		name 'ADC2 Digital Mixer src'
+		value 'ADC2 data'
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 'disable all'
+			item.1 'ADC1 data'
+			item.2 'ADC2 data'
+			item.3 'ADC3 data'
+			item.4 'ADC4 data'
+		}
+	}
+	control.57 {
+		iface MIXER
+		name 'ADC3 Digital Mixer gc'
+		value 'disable all'
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 'disable all'
+			item.1 'ADC1 data'
+			item.2 'ADC2 data'
+			item.3 'ADC3 data'
+			item.4 'ADC4 data'
+		}
+	}
+	control.58 {
+		iface MIXER
+		name 'ADC3 Digital Mixer src'
+		value 'ADC3 data'
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 'disable all'
+			item.1 'ADC1 data'
+			item.2 'ADC2 data'
+			item.3 'ADC3 data'
+			item.4 'ADC4 data'
+		}
+	}
+	control.59 {
+		iface MIXER
+		name 'ADC4 Digital Mixer gc'
+		value 'disable all'
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 'disable all'
+			item.1 'ADC1 data'
+			item.2 'ADC2 data'
+			item.3 'ADC3 data'
+			item.4 'ADC4 data'
+		}
+	}
+	control.60 {
+		iface MIXER
+		name 'ADC4 Digital Mixer src'
+		value 'ADC4 data'
+		comment {
+			access 'read write'
+			type ENUMERATED
+			count 1
+			item.0 'disable all'
+			item.1 'ADC1 data'
+			item.2 'ADC2 data'
+			item.3 'ADC3 data'
+			item.4 'ADC4 data'
+		}
+	}
+}
diff --git a/builddtbo.sh b/builddtbo.sh
index 9404804..22c0046 100755
--- a/builddtbo.sh
+++ b/builddtbo.sh
@@ -2,6 +2,7 @@
 
 dtc -@ -I dts -O dtb -o seeed-2mic-voicecard.dtbo seeed-2mic-voicecard-overlay.dts
 dtc -@ -I dts -O dtb -o seeed-4mic-voicecard.dtbo seeed-4mic-voicecard-overlay.dts
+dtc -@ -I dts -O dtb -o seeed-8mic-voicecard.dtbo seeed-8mic-voicecard-overlay.dts
 
 # cp *.dtbo /boot/overlays
 # dtoverlay seeed-2mic-voicecard
diff --git a/seeed-8mic-voicecard-overlay.dts b/seeed-8mic-voicecard-overlay.dts
new file mode 100644
index 0000000..095ab5e
--- /dev/null
+++ b/seeed-8mic-voicecard-overlay.dts
@@ -0,0 +1,80 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+	compatible = "brcm,bcm2708";
+
+	fragment@0 {
+		target = <&i2s>;
+		__overlay__ {
+			#sound-dai-cells = <0>;
+			status = "okay";
+		};
+	};
+
+	fragment@1 {
+		target-path = "/clocks";
+		__overlay__ {
+			ac108_mclk: codec-mclk {
+				compatible = "fixed-clock";
+				#clock-cells = <0>;
+				clock-frequency = <24000000>;
+			};  
+		};
+	};
+
+	fragment@2 {
+		target = <&i2c1>;
+		__overlay__ {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "okay";
+
+			ac108_a: ac108@35{
+				compatible = "x-power,ac108_0";
+				reg = <0x35>;
+				#sound-dai-cells = <0>;
+				data-protocol = <0>;
+			};
+
+			ac108_b: ac108@3b{
+				compatible = "x-power,ac108_1";
+				reg = <0x3b>;
+				#sound-dai-cells = <0>;
+				data-protocol = <0>;
+			};
+		};
+	};
+
+
+	fragment@3 {
+		target = <&sound>;
+
+		sound_overlay: __overlay__ {
+			compatible = "simple-audio-card";
+			simple-audio-card,format = "dsp_a";
+			simple-audio-card,name = "seeed-8mic-voicecard"; 
+			status = "okay";
+		
+			simple-audio-card,bitclock-master = <&codec_dai>;
+			simple-audio-card,frame-master = <&codec_dai>;
+
+			cpu_dai: simple-audio-card,cpu {
+				sound-dai = <&i2s>;
+				dai-tdm-slot-num     = <2>;
+				dai-tdm-slot-width   = <32>;
+				dai-tdm-slot-tx-mask = <1 1 0 0>;
+				dai-tdm-slot-rx-mask = <1 1 0 0>;
+			};
+			codec_dai: simple-audio-card,codec {
+				sound-dai = <&ac108_b>;
+				clocks =  <&ac108_mclk>;
+			};
+		};
+	};
+
+	__overrides__ {
+		card-name = <&sound_overlay>,"seeed-voicecard,name";
+	};
+};
+
diff --git a/seeed-8mic-voicecard.dtbo b/seeed-8mic-voicecard.dtbo
new file mode 100644
index 0000000..fcd994e
Binary files /dev/null and b/seeed-8mic-voicecard.dtbo differ
diff --git a/simple-card.c b/simple-card.c
index 978decb..afeb840 100644
--- a/simple-card.c
+++ b/simple-card.c
@@ -125,10 +125,10 @@ static int asoc_simple_card_startup(struct snd_pcm_substream *substream)
 	if (ret)
 		clk_disable_unprepare(dai_props->cpu_dai.clk);
 
-	rtd->cpu_dai->driver->playback.channels_min = 4;
-	rtd->cpu_dai->driver->playback.channels_max = 4;
-	rtd->cpu_dai->driver->capture.channels_min = 4;
-	rtd->cpu_dai->driver->capture.channels_max = 4;
+	rtd->cpu_dai->driver->playback.channels_min = 8;
+	rtd->cpu_dai->driver->playback.channels_max = 8;
+	rtd->cpu_dai->driver->capture.channels_min = 8;
+	rtd->cpu_dai->driver->capture.channels_max = 8;
 
 	return ret;
 }