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Move: ac101 pll clock source set to bclk if it's slave mode

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This commit is contained in:
Peter.Yang 2018-03-07 06:34:33 +00:00
parent cff392127f
commit 6b6552bf9c
1 changed files with 25 additions and 18 deletions
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17
ac101.c
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@ -451,22 +451,28 @@ static const struct pll_div codec_pll_div[] = {
{192000, 22579200, 1, 352, 4}, {192000, 22579200, 1, 352, 4},
{256000, 22579200, 1, 264, 3}, {256000, 22579200, 1, 264, 3},
{384000, 22579200, 1, 176, 2},/*((176+2*0.2)*6000000)/(38*(2*1+1))*/ {384000, 22579200, 1, 176, 2},/*((176+2*0.2)*6000000)/(38*(2*1+1))*/
{2822400, 22579200, 1, 24, 0},/* accurate, 11025 * 256 */
{5644800, 22579200, 1, 12, 0},/* accurate, 22050 * 256 */
{6000000, 22579200, 38, 429, 0},/*((429+0*0.2)*6000000)/(38*(2*1+1))*/ {6000000, 22579200, 38, 429, 0},/*((429+0*0.2)*6000000)/(38*(2*1+1))*/
{11289600, 22579200, 1, 6, 0},/* accurate, 44100 * 256 */
{13000000, 22579200, 19, 99, 0}, {13000000, 22579200, 19, 99, 0},
{19200000, 22579200, 25, 88, 1}, {19200000, 22579200, 25, 88, 1},
{24000000, 22579200, 63, 177, 4},/*((177 + 4 * 0.2) * 24000000) / (63 * (2 * 1 + 1)) */ {24000000, 22579200, 63, 177, 4}, /* 22577778 Hz */
{128000, 24576000, 1, 576, 0}, {128000, 24576000, 1, 576, 0},
{192000, 24576000, 1, 384, 0}, {192000, 24576000, 1, 384, 0},
{256000, 24576000, 1, 288, 0}, {256000, 24576000, 1, 288, 0},
{384000, 24576000, 1, 192, 0}, {384000, 24576000, 1, 192, 0},
{1411200, 22579200, 1, 48, 0}, {1411200, 22579200, 1, 48, 0},
{2048000, 24576000, 1, 36, 0}, {2048000, 24576000, 1, 36, 0}, /* accurate, 8000 * 256 */
{3072000, 24576000, 1, 24, 0}, /* accurate, 12000 * 256 */
{4096000, 24576000, 1, 18, 0}, /* accurate, 16000 * 256 */
{6000000, 24576000, 25, 307, 1}, {6000000, 24576000, 25, 307, 1},
{6144000, 24576000, 1, 12, 0}, /* accurate, 24000 * 256 */
{12288000, 24576000, 1, 6, 0}, /* accurate, 48000 * 256 */
{13000000, 24576000, 42, 238, 1}, {13000000, 24576000, 42, 238, 1},
{19200000, 24576000, 25, 96, 0}, {19200000, 24576000, 25, 96, 0},
{24000000, 24576000, 25, 76, 4},/* accurate */ {24000000, 24576000, 25, 76, 4},/* accurate */
{11289600, 22579200, 1, 6, 0},
{12288000, 24576000, 1, 6, 0},
}; };
static const struct aif1_fs codec_aif1_fs[] = { static const struct aif1_fs codec_aif1_fs[] = {
@ -707,7 +713,8 @@ int ac101_hw_params(struct snd_pcm_substream *substream,
} }
ac101_update_bits(codec, AIF_CLK_CTRL, (0xf<<AIF1_BCLK_DIV), i<<AIF1_BCLK_DIV); ac101_update_bits(codec, AIF_CLK_CTRL, (0xf<<AIF1_BCLK_DIV), i<<AIF1_BCLK_DIV);
} else { } else {
ac101_set_pll(codec_dai, AC101_MCLK1, 0, ac10x->sysclk, freq_out); /* set pll clock source to BCLK if slave mode */
ac101_set_pll(codec_dai, AC101_BCLK1, 0, aif1_lrck_div * params_rate(params), freq_out);
} }
AC101_DBG("rate: %d , channels: %d , samp_res: %d", AC101_DBG("rate: %d , channels: %d , samp_res: %d",