Fix: ac101 noise import by PLL frequncy deviation
This commit is contained in:
Peter.Yang
parent
0d30a1599d
commit
cff392127f
2 changed files with 44 additions and 28 deletions
19
ac101.c
19
ac101.c
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@ -442,8 +442,9 @@ struct kv_map {
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};
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/*
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* Note : pll code from original tdm/i2s driver.
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* freq_out = freq_in * N/(m*(2k+1)) , k=1,N=N_i+N_f,N_f=factor*0.2;
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* Note : pll code from original tdm/i2s driver.
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* freq_out = freq_in * N/(M*(2k+1)) , k=1,N=N_i+N_f,N_f=factor*0.2;
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* N_i[0,1023], N_f_factor[0,7], m[1,64]=REG_VAL[1-63,0]
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*/
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static const struct pll_div codec_pll_div[] = {
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{128000, 22579200, 1, 529, 1},
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@ -463,7 +464,7 @@ static const struct pll_div codec_pll_div[] = {
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{6000000, 24576000, 25, 307, 1},
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{13000000, 24576000, 42, 238, 1},
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{19200000, 24576000, 25, 96, 0},
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{24000000, 24576000, 39, 119, 4},/*((119 + 4 * 0.2) * 24000000) / (39 * (2 * 1 + 1)) */
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{24000000, 24576000, 25, 76, 4},/* accurate */
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{11289600, 22579200, 1, 6, 0},
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{12288000, 24576000, 1, 6, 0},
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};
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@ -536,8 +537,10 @@ int ac101_aif_mute(struct snd_soc_dai *codec_dai, int mute)
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ac101_headphone_event(codec, SND_SOC_DAPM_PRE_PMD);
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late_enable_dac(codec, SND_SOC_DAPM_POST_PMD);
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#if _MASTER_MULTI_CODEC != _MASTER_AC101
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ac10x->aif1_clken = 1;
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ac101_aif1clk(codec, SND_SOC_DAPM_POST_PMD);
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#endif
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}
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return 0;
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}
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@ -604,6 +607,7 @@ static int ac101_set_pll(struct snd_soc_dai *codec_dai, int pll_id, int source,
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}
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}
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/*config pll m*/
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if (m == 64) m = 0;
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ac101_update_bits(codec, PLL_CTRL1, (0x3f<<PLL_POSTDIV_M), (m<<PLL_POSTDIV_M));
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/*config pll n*/
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ac101_update_bits(codec, PLL_CTRL2, (0x3ff<<PLL_PREDIV_NI), (n_i<<PLL_PREDIV_NI));
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@ -702,6 +706,8 @@ int ac101_hw_params(struct snd_pcm_substream *substream,
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}
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}
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ac101_update_bits(codec, AIF_CLK_CTRL, (0xf<<AIF1_BCLK_DIV), i<<AIF1_BCLK_DIV);
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} else {
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ac101_set_pll(codec_dai, AC101_MCLK1, 0, ac10x->sysclk, freq_out);
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}
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AC101_DBG("rate: %d , channels: %d , samp_res: %d",
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@ -766,6 +772,10 @@ int ac101_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
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case SND_SOC_DAIFMT_DSP_A: /* L reg_val msb after FRM LRC */
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reg_val |= (0x3<<AIF1_DATA_FMT);
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break;
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case SND_SOC_DAIFMT_DSP_B:
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/* TODO: data offset set to 0 */
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reg_val |= (0x3<<AIF1_DATA_FMT);
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break;
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default:
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pr_err("%s, line:%d\n", __func__, __LINE__);
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return -EINVAL;
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@ -814,6 +824,9 @@ static int ac101_set_clock(int y_start_n_stop) {
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if (y_start_n_stop) {
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/* enable global clock */
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ac101_aif1clk(static_ac10x->codec, SND_SOC_DAPM_PRE_PMU);
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} else {
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static_ac10x->aif1_clken = 1;
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ac101_aif1clk(static_ac10x->codec, SND_SOC_DAPM_POST_PMD);
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}
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return 0;
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}
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53
ac108.c
53
ac108.c
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@ -104,7 +104,7 @@ static const struct pll_div ac108_pll_div_list[] = {
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{ 16000000, 24576000, 12, 0, 400, 9, 1 },
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{ 19200000, 24576000, 15, 0, 410, 9, 1 },
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{ 19680000, 24576000, 15, 0, 400, 9, 1 },
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{ 24000000, 24576000, 9, 0, 205, 9, 1 },
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{ 24000000, 24576000, 4, 0, 128,24, 0 }, //accurate
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{ 400000, 22579200, 0, 0, 566, 4, 1 },
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{ 512000, 22579200, 0, 0, 880, 9, 1 },
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@ -122,7 +122,7 @@ static const struct pll_div ac108_pll_div_list[] = {
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{ 16000000, 22579200, 11, 0, 340, 9, 1 },
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{ 19200000, 22579200, 13, 0, 330, 9, 1 },
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{ 19680000, 22579200, 14, 0, 345, 9, 1 },
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{ 24000000, 22579200, 16, 0, 320, 9, 1 },
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{ 24000000, 22579200, 24, 0, 588,24, 0 }, // accurate
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{ 12288000, 24576000, 9, 0, 400, 9, 1 }, //24576000/2
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{ 11289600, 22579200, 9, 0, 400, 9, 1 }, //22579200/2
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@ -216,12 +216,11 @@ static int snd_ac108_get_volsw(struct snd_kcontrol *kcontrol,
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if ((ret = ac10x_read(mc->reg, &val, ac10x->i2cmap[chip])) < 0)
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return ret;
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val = (val >> mc->shift) & mask;
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ucontrol->value.integer.value[0] = val - mc->min;
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val = ((val >> mc->shift) & mask) - mc->min;
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if (invert) {
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ucontrol->value.integer.value[0] =
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mc->max - ucontrol->value.integer.value[0];
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val = mc->max - val;
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}
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ucontrol->value.integer.value[0] = val;
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return 0;
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}
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@ -532,7 +531,7 @@ static int ac108_configure_clocking(struct ac10x_priv *ac10x, unsigned int rate)
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ac108_multi_chips_update_bits(PLL_CTRL4, 0xff << PLL_LOOPDIV_LSB, (unsigned char)ac108_pll_div.n << PLL_LOOPDIV_LSB, ac10x);
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ac108_multi_chips_update_bits(PLL_CTRL3, 0x03 << PLL_LOOPDIV_MSB, (ac108_pll_div.n >> 8) << PLL_LOOPDIV_MSB, ac10x);
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ac108_multi_chips_update_bits(PLL_CTRL2, 0x1f << PLL_PREDIV1 | 0x01 << PLL_PREDIV2,
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ac108_pll_div.m1 << PLL_PREDIV1 | ac108_pll_div.m2 << PLL_PREDIV2, ac10x);
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ac108_pll_div.m1 << PLL_PREDIV1 | ac108_pll_div.m2 << PLL_PREDIV2, ac10x);
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/*0x18: PLL clk lock enable*/
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ac108_multi_chips_update_bits(PLL_LOCK_CTRL, 0x1 << PLL_LOCK_EN, 0x1 << PLL_LOCK_EN, ac10x);
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@ -545,7 +544,7 @@ static int ac108_configure_clocking(struct ac10x_priv *ac10x, unsigned int rate)
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* pll,enable sysclk
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*/
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ac108_multi_chips_update_bits(SYSCLK_CTRL, 0x01 << PLLCLK_EN | 0x03 << PLLCLK_SRC | 0x01 << SYSCLK_SRC | 0x01 << SYSCLK_EN,
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0x01 << PLLCLK_EN | 0x00 << PLLCLK_SRC | 0x01 << SYSCLK_SRC | 0x01 << SYSCLK_EN, ac10x);
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0x01 << PLLCLK_EN | 0x00 << PLLCLK_SRC | 0x01 << SYSCLK_SRC | 0x01 << SYSCLK_EN, ac10x);
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ac10x->mclk = ac108_pll_div.freq_out;
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}
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if (ac10x->clk_id == SYSCLK_SRC_MCLK) {
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@ -725,9 +724,12 @@ static int ac108_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_h
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}
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} else {
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unsigned div;
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/*TDM mode or normal mode*/
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ac108_multi_chips_write(I2S_LRCK_CTRL2, ac108_samp_res[samp_res].real_val * channels - 1, ac10x);
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ac108_multi_chips_update_bits(I2S_LRCK_CTRL1, 0x03 << 0, 0x00, ac10x);
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div = ac108_samp_res[samp_res].real_val * channels - 1;
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ac108_multi_chips_write(I2S_LRCK_CTRL2, (div & 0xFF), ac10x);
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ac108_multi_chips_update_bits(I2S_LRCK_CTRL1, 0x03 << 0, (div >> 8) << 0, ac10x);
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}
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/**
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@ -819,7 +821,7 @@ static int ac108_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) {
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* 0x30:chip is master mode ,BCLK & LRCK output
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*/
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ac108_multi_chips_update_bits(I2S_CTRL, 0x03 << LRCK_IOEN | 0x03 << SDO1_EN | 0x1 << TXEN | 0x1 << GEN,
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0x00 << LRCK_IOEN | 0x03 << SDO1_EN | 0x1 << TXEN | 0x1 << GEN, ac10x);
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0x00 << LRCK_IOEN | 0x03 << SDO1_EN | 0x1 << TXEN | 0x1 << GEN, ac10x);
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/* multi_chips: only one chip set as Master, and the others also need to set as Slave */
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ac10x_update_bits(I2S_CTRL, 0x3 << LRCK_IOEN, 0x2 << LRCK_IOEN, ac10x->i2cmap[_MASTER_INDEX]);
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break;
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@ -869,11 +871,10 @@ static int ac108_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) {
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tx_offset = 0;
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break;
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default:
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ac10x->i2s_mode = LEFT_JUSTIFIED_FORMAT;
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tx_offset = 1;
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return -EINVAL;
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pr_err("AC108 I2S format config error:%u\n\n", fmt & SND_SOC_DAIFMT_FORMAT_MASK);
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return -EINVAL;
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}
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/*AC108 config BCLK&LRCK polarity*/
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switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
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case SND_SOC_DAIFMT_NB_NF:
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@ -912,7 +913,7 @@ static int ac108_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) {
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/**
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*0x31: 0: normal mode, negative edge drive and positive edge sample
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1: invert mode, positive edge drive and negative edge sample
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1: invert mode, positive edge drive and negative edge sample
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*/
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ac108_multi_chips_update_bits(I2S_BCLK_CTRL, 0x01 << BCLK_POLARITY, brck_polarity << BCLK_POLARITY, ac10x);
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/**
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@ -957,6 +958,7 @@ static int ac108_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) {
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/*
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* due to miss channels order in cpu_dai, we meed defer the clock starting.
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*/
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#if _MASTER_MULTI_CODEC == _MASTER_AC108
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static int ac108_set_clock(int y_start_n_stop) {
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u8 r;
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@ -983,6 +985,7 @@ static int ac108_set_clock(int y_start_n_stop) {
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return 0;
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}
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#endif
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static int ac108_trigger(struct snd_pcm_substream *substream, int cmd,
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struct snd_soc_dai *dai)
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@ -1001,18 +1004,18 @@ static int ac108_trigger(struct snd_pcm_substream *substream, int cmd,
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case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
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/* disable global clock if lrck disabled */
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ac10x_read(I2S_CTRL, &r, ac10x->i2cmap[_MASTER_INDEX]);
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if ((r & (0x01 << LRCK_IOEN)) == 0) {
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if ((r & (0x02 << LRCK_IOEN)) && (r & (0x01 << LRCK_IOEN)) == 0) {
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/* disable global clock */
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ac108_multi_chips_update_bits(I2S_CTRL, 0x1 << TXEN | 0x1 << GEN, 0x1 << TXEN | 0x0 << GEN, ac10x);
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/*0x21: Module clock enable<I2S, ADC digital, MIC offset Calibration, ADC analog>*/
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ac108_multi_chips_write(MOD_CLK_EN, 1 << I2S | 1 << ADC_DIGITAL | 1 << MIC_OFFSET_CALIBRATION | 1 << ADC_ANALOG, ac10x);
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/*0x22: Module reset de-asserted<I2S, ADC digital, MIC offset Calibration, ADC analog>*/
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ac108_multi_chips_write(MOD_RST_CTRL, 1 << I2S | 1 << ADC_DIGITAL | 1 << MIC_OFFSET_CALIBRATION | 1 << ADC_ANALOG, ac10x);
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/* delayed clock starting, move to simple_card_trigger() */
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}
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/*0x21: Module clock enable<I2S, ADC digital, MIC offset Calibration, ADC analog>*/
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ac108_multi_chips_write(MOD_CLK_EN, 1 << I2S | 1 << ADC_DIGITAL | 1 << MIC_OFFSET_CALIBRATION | 1 << ADC_ANALOG, ac10x);
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/*0x22: Module reset de-asserted<I2S, ADC digital, MIC offset Calibration, ADC analog>*/
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ac108_multi_chips_write(MOD_RST_CTRL, 1 << I2S | 1 << ADC_DIGITAL | 1 << MIC_OFFSET_CALIBRATION | 1 << ADC_ANALOG, ac10x);
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/* delayed clock starting, move to simple_card_trigger() */
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break;
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case SNDRV_PCM_TRIGGER_STOP:
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case SNDRV_PCM_TRIGGER_SUSPEND:
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@ -1342,7 +1345,7 @@ static int ac108_i2c_probe(struct i2c_client *i2c, const struct i2c_device_id *i
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if (of_property_read_u32(np, "tdm-chips-count", &val)) val = 1;
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ac10x->tdm_chips_cnt = val;
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pr_err(" i2c_id number : %d\n", index);
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pr_err(" ac10x i2c_id number: %d\n", index);
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pr_err(" ac10x data protocol: %d\n", ac10x->data_protocol);
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ac10x->i2c[index] = i2c;
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