pcm format 8 channels, using two ac108 chips
This commit is contained in:
peter.yang
parent
7f4b5849a7
commit
5028a91201
6 changed files with 1097 additions and 17 deletions
72
ac108.c
72
ac108.c
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@ -22,7 +22,6 @@
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#include <sound/soc.h>
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#include <sound/initval.h>
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#include <sound/tlv.h>
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#include <sound/wm8960.h>
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#include "ac108.h"
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@ -755,6 +754,34 @@ static int ac108_configure_clocking(struct ac108_priv *ac108, unsigned int rate)
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return 0;
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}
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/*
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* support no more than 16 slots.
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*/
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static int ac108_multi_chips_slots(struct ac108_priv *ac, int slots) {
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int i;
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/* codec0 enable slots 1,2,3,4
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* codec1 enable slots 5,6,7,8 etc
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*/
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for (i = 0; i < ac->codec_index; i++) {
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unsigned vec;
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/* 0x38-0x3A I2S_TX1_CTRLx */
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vec = 0xFUL << (i << 2);
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ac108_write(I2S_TX1_CTRL1, slots - 1, ac->i2c[i]);
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ac108_write(I2S_TX1_CTRL2, (vec >> 0) & 0xFF, ac->i2c[i]);
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ac108_write(I2S_TX1_CTRL3, (vec >> 8) & 0xFF, ac->i2c[i]);
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/* 0x3C-0x3F I2S_TX1_CHMP_CTRLx */
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vec = (0x0 << 0 | 0x1 << 2 | 0x2 << 4 | 0x3 << 6) << (i << 3);
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ac108_write(I2S_TX1_CHMP_CTRL1, (vec >> 0) & 0xFF, ac->i2c[i]);
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ac108_write(I2S_TX1_CHMP_CTRL2, (vec >> 8) & 0xFF, ac->i2c[i]);
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ac108_write(I2S_TX1_CHMP_CTRL3, (vec >> 16) & 0xFF, ac->i2c[i]);
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ac108_write(I2S_TX1_CHMP_CTRL4, (vec >> 24) & 0xFF, ac->i2c[i]);
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}
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return 0;
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}
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static int ac108_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) {
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unsigned int i, channels, sample_resolution, rate;
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struct snd_soc_codec *codec = dai->codec;
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@ -867,8 +894,12 @@ static int ac108_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_h
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break;
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}
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}
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ac108_multi_chips_update_bits(I2S_BCLK_CTRL, 0x0F << BCLKDIV, i << BCLKDIV, ac108);
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/*
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* slots allocation for each chip
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*/
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ac108_multi_chips_slots(ac108, channels);
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return 0;
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}
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@ -910,6 +941,8 @@ static int ac108_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) {
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unsigned char tx_offset, lrck_polarity, brck_polarity;
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struct ac108_priv *ac108 = dev_get_drvdata(dai->dev);
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int i;
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switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
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case SND_SOC_DAIFMT_CBM_CFM: /*AC108 Master*/
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dev_dbg(dai->dev, "AC108 set to work as Master\n");
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@ -919,8 +952,9 @@ static int ac108_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) {
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ac108_multi_chips_update_bits(I2S_CTRL, 0x03 << LRCK_IOEN | 0x03 << SDO1_EN | 0x1 << TXEN | 0x1 << GEN,
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0x03 << LRCK_IOEN | 0x03 << SDO1_EN | 0x1 << TXEN | 0x1 << GEN, ac108);
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/* multi_chips: only one chip set as Master, and the others also need to set as Slave */
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if (ac108->codec_index > 1) ac108_update_bits(I2S_CTRL, 0x3 << LRCK_IOEN, 0x0 << LRCK_IOEN, ac108->i2c[1]);
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for (i = 1; i < ac108->codec_index; i++) {
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ac108_update_bits(I2S_CTRL, 0x3 << LRCK_IOEN, 0x0 << LRCK_IOEN, ac108->i2c[i]);
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}
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break;
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case SND_SOC_DAIFMT_CBS_CFS: /*AC108 Slave*/
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dev_dbg(dai->dev, "AC108 set to work as Slave\n");
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@ -1183,7 +1217,7 @@ static const struct snd_soc_codec_driver ac108_soc_codec_driver = {
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static ssize_t ac108_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) {
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int val = 0, flag = 0;
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u8 i = 0, reg, num, value_w, value_r;
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u8 i = 0, reg, num, value_w, value_r[4];
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val = simple_strtol(buf, NULL, 16);
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flag = (val >> 16) & 0xF;
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@ -1199,12 +1233,23 @@ static ssize_t ac108_store(struct device *dev, struct device_attribute *attr, co
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printk("\nRead: start REG:0x%02x,count:0x%02x\n", reg, num);
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do {
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value_r = 0;
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ac108_multi_chips_read(reg, &value_r, ac108);
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printk("REG[0x%02x]: 0x%02x; ", reg, value_r);
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int k;
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memset(value_r, 0, sizeof value_r);
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for (k = 0; k < ac108->codec_index; k++) {
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ac108_read(reg, &value_r[k], ac108->i2c[k]);
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}
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if (ac108->codec_index >= 2) {
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printk("REG[0x%02x]: 0x%02x 0x%02x", reg, value_r[0], value_r[1]);
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} else {
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printk("REG[0x%02x]: 0x%02x", reg, value_r[0]);
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}
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reg++;
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i++;
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if ((i == num) || (i % 4 == 0)) printk("\n");
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if ((++i == num) || (i % 4 == 0)) {
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printk("\n");
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}
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} while (i < num);
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}
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@ -1261,6 +1306,10 @@ static int ac108_i2c_probe(struct i2c_client *i2c,
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ac108->data_protocol = val;
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/*Writing this register 0x12 resets all register to their default state.*/
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ac108_write(CHIP_RST, CHIP_RST_VAL, i2c);
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msleep(1);
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pr_err(" i2c_id number :%d\n", (int)(i2c_id->driver_data));
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pr_err(" ac108 codec_index :%d\n", ac108->codec_index);
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pr_err(" ac108 I2S data protocol type :%d\n", ac108->data_protocol);
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@ -1275,9 +1324,6 @@ static int ac108_i2c_probe(struct i2c_client *i2c,
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ac108->codec_index++;
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/*Writing this register 0x12 resets all register to their default state.*/
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ac108_write(CHIP_RST, CHIP_RST_VAL, i2c);
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ret = sysfs_create_group(&i2c->dev.kobj, &ac108_debug_attr_group);
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if (ret) {
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pr_err("failed to create attr group\n");
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953
ac108_8mic.state
Normal file
953
ac108_8mic.state
Normal file
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@ -0,0 +1,953 @@
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state.ALSA {
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control.1 {
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iface MIXER
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name 'PCM Playback Volume'
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value 400
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comment {
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access 'read write'
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type INTEGER
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count 1
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range '-10239 - 400'
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dbmin -9999999
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dbmax 400
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dbvalue.0 400
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}
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}
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control.2 {
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iface MIXER
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name 'PCM Playback Switch'
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value true
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comment {
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access 'read write'
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type BOOLEAN
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count 1
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}
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}
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control.3 {
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iface MIXER
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name 'PCM Playback Route'
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value 0
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comment {
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access 'read write'
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type INTEGER
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count 1
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range '0 - 2'
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}
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}
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control.4 {
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iface PCM
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name 'IEC958 Playback Default'
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value '0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000'
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comment {
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access 'read write'
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type IEC958
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count 1
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}
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}
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control.5 {
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iface PCM
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name 'IEC958 Playback Con Mask'
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value '0200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000'
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comment {
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access read
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type IEC958
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count 1
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}
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}
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control.6 {
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iface PCM
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name 'IEC958 Playback PCM Stream'
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value '0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000'
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comment {
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access 'read write inactive'
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type IEC958
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count 1
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}
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}
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}
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state.seeed8micvoicec {
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control.1 {
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iface MIXER
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name 'OUT1 Mute'
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value false
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comment {
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access 'read write'
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type BOOLEAN
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count 1
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}
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}
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control.2 {
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iface MIXER
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name 'OUT2 Mute'
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value true
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comment {
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access 'read write'
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type BOOLEAN
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count 1
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}
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}
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control.3 {
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iface MIXER
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name 'TX1 Channel1~8 enable'
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value '1-4 channels '
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comment {
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access 'read write'
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type ENUMERATED
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count 1
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item.0 'disable all'
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item.1 '1-1 channels '
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item.2 '1-2 channels '
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item.3 '1-3 channels '
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item.4 '1-4 channels '
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item.5 '1-5 channels '
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item.6 '1-6 channels '
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item.7 '1-7 channels '
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item.8 '1-8 channels '
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}
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}
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control.4 {
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iface MIXER
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name 'TX1 Channel9~16 enable'
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value 'disable all'
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comment {
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access 'read write'
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type ENUMERATED
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count 1
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item.0 'disable all'
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item.1 '8-9 channels '
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item.2 '8-10 channels '
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item.3 '8-11 channels '
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item.4 '8-12 channels '
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item.5 '8-13 channels '
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item.6 '8-14 channels '
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item.7 '8-15 channels '
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item.8 '8-16 channels '
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}
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}
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control.5 {
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iface MIXER
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name 'TX2 Channel1~8 enable'
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value 'disable all'
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comment {
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access 'read write'
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type ENUMERATED
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count 1
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item.0 'disable all'
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item.1 '1-1 channels '
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item.2 '1-2 channels '
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item.3 '1-3 channels '
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item.4 '1-4 channels '
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item.5 '1-5 channels '
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item.6 '1-6 channels '
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item.7 '1-7 channels '
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item.8 '1-8 channels '
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}
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}
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control.6 {
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iface MIXER
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name 'TX2 Channel9~16 enable'
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value 'disable all'
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comment {
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access 'read write'
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type ENUMERATED
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count 1
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item.0 'disable all'
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item.1 '8-9 channels '
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item.2 '8-10 channels '
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item.3 '8-11 channels '
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item.4 '8-12 channels '
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item.5 '8-13 channels '
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item.6 '8-14 channels '
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item.7 '8-15 channels '
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item.8 '8-16 channels '
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}
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}
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control.7 {
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iface MIXER
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name 'CH1 digital volume'
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value 181
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comment {
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access 'read write'
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type INTEGER
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count 1
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range '0 - 255'
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dbmin -11925
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dbmax 7200
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dbvalue.0 1650
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}
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}
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control.8 {
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iface MIXER
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name 'CH2 digital volume'
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value 181
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comment {
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access 'read write'
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type INTEGER
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count 1
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range '0 - 255'
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dbmin -11925
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dbmax 7200
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dbvalue.0 1650
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}
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}
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control.9 {
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iface MIXER
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name 'CH3 digital volume'
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value 181
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comment {
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access 'read write'
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type INTEGER
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count 1
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range '0 - 255'
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dbmin -11925
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dbmax 7200
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dbvalue.0 1650
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}
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}
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control.10 {
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iface MIXER
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name 'CH4 digital volume'
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value 181
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comment {
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access 'read write'
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type INTEGER
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count 1
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range '0 - 255'
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dbmin -11925
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dbmax 7200
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dbvalue.0 1650
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}
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}
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control.11 {
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iface MIXER
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name 'ADC1 PGA gain'
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value 27
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comment {
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access 'read write'
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type INTEGER
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count 1
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range '0 - 31'
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dbmin 0
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dbmax 3100
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dbvalue.0 2700
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}
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}
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control.12 {
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iface MIXER
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name 'ADC2 PGA gain'
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value 27
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comment {
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access 'read write'
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type INTEGER
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count 1
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range '0 - 31'
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dbmin 0
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dbmax 3100
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dbvalue.0 2700
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}
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}
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control.13 {
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iface MIXER
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name 'ADC3 PGA gain'
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value 27
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comment {
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access 'read write'
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type INTEGER
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count 1
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range '0 - 31'
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dbmin 0
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dbmax 3100
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dbvalue.0 2700
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}
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}
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control.14 {
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iface MIXER
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name 'ADC4 PGA gain'
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value 27
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comment {
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access 'read write'
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type INTEGER
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count 1
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range '0 - 31'
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dbmin 0
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dbmax 3100
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dbvalue.0 2700
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}
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}
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control.15 {
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iface MIXER
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name 'Tx1 Channels'
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value '4 channels '
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comment {
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access 'read write'
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type ENUMERATED
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count 1
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item.0 '1 channels '
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item.1 '2 channels '
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item.2 '3 channels '
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item.3 '4 channels '
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item.4 '5 channels '
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item.5 '6 channels '
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item.6 '7 channels '
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item.7 '8 channels '
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item.8 '9 channels '
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item.9 '10 channels '
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item.10 '11 channels '
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item.11 '12 channels '
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item.12 '13 channels '
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item.13 '14 channels '
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item.14 '15 channels '
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item.15 '16 channels '
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}
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}
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control.16 {
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iface MIXER
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name 'Tx2 Channels'
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value '1 channels '
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comment {
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access 'read write'
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type ENUMERATED
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count 1
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item.0 '1 channels '
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item.1 '2 channels '
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item.2 '3 channels '
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item.3 '4 channels '
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item.4 '5 channels '
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item.5 '6 channels '
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item.6 '7 channels '
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item.7 '8 channels '
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item.8 '9 channels '
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item.9 '10 channels '
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item.10 '11 channels '
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item.11 '12 channels '
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item.12 '13 channels '
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item.13 '14 channels '
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item.14 '15 channels '
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item.15 '16 channels '
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}
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}
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control.17 {
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iface MIXER
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name 'Tx1 Channels 1 MAP'
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value '1st adc sample'
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comment {
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access 'read write'
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type ENUMERATED
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count 1
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item.0 '1st adc sample'
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item.1 '2st adc sample'
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item.2 '3st adc sample'
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item.3 '4st adc sample'
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}
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}
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control.18 {
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iface MIXER
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name 'Tx1 Channels 2 MAP'
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value '2st adc sample'
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comment {
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access 'read write'
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type ENUMERATED
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count 1
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item.0 '1st adc sample'
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item.1 '2st adc sample'
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item.2 '3st adc sample'
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item.3 '4st adc sample'
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}
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}
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control.19 {
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iface MIXER
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name 'Tx1 Channels 3 MAP'
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||||
value '3st adc sample'
|
||||
comment {
|
||||
access 'read write'
|
||||
type ENUMERATED
|
||||
count 1
|
||||
item.0 '1st adc sample'
|
||||
item.1 '2st adc sample'
|
||||
item.2 '3st adc sample'
|
||||
item.3 '4st adc sample'
|
||||
}
|
||||
}
|
||||
control.20 {
|
||||
iface MIXER
|
||||
name 'Tx1 Channels 4 MAP'
|
||||
value '4st adc sample'
|
||||
comment {
|
||||
access 'read write'
|
||||
type ENUMERATED
|
||||
count 1
|
||||
item.0 '1st adc sample'
|
||||
item.1 '2st adc sample'
|
||||
item.2 '3st adc sample'
|
||||
item.3 '4st adc sample'
|
||||
}
|
||||
}
|
||||
control.21 {
|
||||
iface MIXER
|
||||
name 'Tx1 Channels 5 MAP'
|
||||
value '1st adc sample'
|
||||
comment {
|
||||
access 'read write'
|
||||
type ENUMERATED
|
||||
count 1
|
||||
item.0 '1st adc sample'
|
||||
item.1 '2st adc sample'
|
||||
item.2 '3st adc sample'
|
||||
item.3 '4st adc sample'
|
||||
}
|
||||
}
|
||||
control.22 {
|
||||
iface MIXER
|
||||
name 'Tx1 Channels 6 MAP'
|
||||
value '1st adc sample'
|
||||
comment {
|
||||
access 'read write'
|
||||
type ENUMERATED
|
||||
count 1
|
||||
item.0 '1st adc sample'
|
||||
item.1 '2st adc sample'
|
||||
item.2 '3st adc sample'
|
||||
item.3 '4st adc sample'
|
||||
}
|
||||
}
|
||||
control.23 {
|
||||
iface MIXER
|
||||
name 'Tx1 Channels 7 MAP'
|
||||
value '1st adc sample'
|
||||
comment {
|
||||
access 'read write'
|
||||
type ENUMERATED
|
||||
count 1
|
||||
item.0 '1st adc sample'
|
||||
item.1 '2st adc sample'
|
||||
item.2 '3st adc sample'
|
||||
item.3 '4st adc sample'
|
||||
}
|
||||
}
|
||||
control.24 {
|
||||
iface MIXER
|
||||
name 'Tx1 Channels 8 MAP'
|
||||
value '1st adc sample'
|
||||
comment {
|
||||
access 'read write'
|
||||
type ENUMERATED
|
||||
count 1
|
||||
item.0 '1st adc sample'
|
||||
item.1 '2st adc sample'
|
||||
item.2 '3st adc sample'
|
||||
item.3 '4st adc sample'
|
||||
}
|
||||
}
|
||||
control.25 {
|
||||
iface MIXER
|
||||
name 'Tx1 Channels 9 MAP'
|
||||
value '1st adc sample'
|
||||
comment {
|
||||
access 'read write'
|
||||
type ENUMERATED
|
||||
count 1
|
||||
item.0 '1st adc sample'
|
||||
item.1 '2st adc sample'
|
||||
item.2 '3st adc sample'
|
||||
item.3 '4st adc sample'
|
||||
}
|
||||
}
|
||||
control.26 {
|
||||
iface MIXER
|
||||
name 'Tx1 Channels 10 MAP'
|
||||
value '1st adc sample'
|
||||
comment {
|
||||
access 'read write'
|
||||
type ENUMERATED
|
||||
count 1
|
||||
item.0 '1st adc sample'
|
||||
item.1 '2st adc sample'
|
||||
item.2 '3st adc sample'
|
||||
item.3 '4st adc sample'
|
||||
}
|
||||
}
|
||||
control.27 {
|
||||
iface MIXER
|
||||
name 'Tx1 Channels 11 MAP'
|
||||
value '1st adc sample'
|
||||
comment {
|
||||
access 'read write'
|
||||
type ENUMERATED
|
||||
count 1
|
||||
item.0 '1st adc sample'
|
||||
item.1 '2st adc sample'
|
||||
item.2 '3st adc sample'
|
||||
item.3 '4st adc sample'
|
||||
}
|
||||
}
|
||||
control.28 {
|
||||
iface MIXER
|
||||
name 'Tx1 Channels 12 MAP'
|
||||
value '1st adc sample'
|
||||
comment {
|
||||
access 'read write'
|
||||
type ENUMERATED
|
||||
count 1
|
||||
item.0 '1st adc sample'
|
||||
item.1 '2st adc sample'
|
||||
item.2 '3st adc sample'
|
||||
item.3 '4st adc sample'
|
||||
}
|
||||
}
|
||||
control.29 {
|
||||
iface MIXER
|
||||
name 'Tx1 Channels 13 MAP'
|
||||
value '1st adc sample'
|
||||
comment {
|
||||
access 'read write'
|
||||
type ENUMERATED
|
||||
count 1
|
||||
item.0 '1st adc sample'
|
||||
item.1 '2st adc sample'
|
||||
item.2 '3st adc sample'
|
||||
item.3 '4st adc sample'
|
||||
}
|
||||
}
|
||||
control.30 {
|
||||
iface MIXER
|
||||
name 'Tx1 Channels 14 MAP'
|
||||
value '1st adc sample'
|
||||
comment {
|
||||
access 'read write'
|
||||
type ENUMERATED
|
||||
count 1
|
||||
item.0 '1st adc sample'
|
||||
item.1 '2st adc sample'
|
||||
item.2 '3st adc sample'
|
||||
item.3 '4st adc sample'
|
||||
}
|
||||
}
|
||||
control.31 {
|
||||
iface MIXER
|
||||
name 'Tx1 Channels 15 MAP'
|
||||
value '1st adc sample'
|
||||
comment {
|
||||
access 'read write'
|
||||
type ENUMERATED
|
||||
count 1
|
||||
item.0 '1st adc sample'
|
||||
item.1 '2st adc sample'
|
||||
item.2 '3st adc sample'
|
||||
item.3 '4st adc sample'
|
||||
}
|
||||
}
|
||||
control.32 {
|
||||
iface MIXER
|
||||
name 'Tx1 Channels 16 MAP'
|
||||
value '1st adc sample'
|
||||
comment {
|
||||
access 'read write'
|
||||
type ENUMERATED
|
||||
count 1
|
||||
item.0 '1st adc sample'
|
||||
item.1 '2st adc sample'
|
||||
item.2 '3st adc sample'
|
||||
item.3 '4st adc sample'
|
||||
}
|
||||
}
|
||||
control.33 {
|
||||
iface MIXER
|
||||
name 'Tx2 Channels 1 MAP'
|
||||
value '1st adc sample'
|
||||
comment {
|
||||
access 'read write'
|
||||
type ENUMERATED
|
||||
count 1
|
||||
item.0 '1st adc sample'
|
||||
item.1 '2st adc sample'
|
||||
item.2 '3st adc sample'
|
||||
item.3 '4st adc sample'
|
||||
}
|
||||
}
|
||||
control.34 {
|
||||
iface MIXER
|
||||
name 'Tx2 Channels 2 MAP'
|
||||
value '1st adc sample'
|
||||
comment {
|
||||
access 'read write'
|
||||
type ENUMERATED
|
||||
count 1
|
||||
item.0 '1st adc sample'
|
||||
item.1 '2st adc sample'
|
||||
item.2 '3st adc sample'
|
||||
item.3 '4st adc sample'
|
||||
}
|
||||
}
|
||||
control.35 {
|
||||
iface MIXER
|
||||
name 'Tx2 Channels 3 MAP'
|
||||
value '1st adc sample'
|
||||
comment {
|
||||
access 'read write'
|
||||
type ENUMERATED
|
||||
count 1
|
||||
item.0 '1st adc sample'
|
||||
item.1 '2st adc sample'
|
||||
item.2 '3st adc sample'
|
||||
item.3 '4st adc sample'
|
||||
}
|
||||
}
|
||||
control.36 {
|
||||
iface MIXER
|
||||
name 'Tx2 Channels 4 MAP'
|
||||
value '1st adc sample'
|
||||
comment {
|
||||
access 'read write'
|
||||
type ENUMERATED
|
||||
count 1
|
||||
item.0 '1st adc sample'
|
||||
item.1 '2st adc sample'
|
||||
item.2 '3st adc sample'
|
||||
item.3 '4st adc sample'
|
||||
}
|
||||
}
|
||||
control.37 {
|
||||
iface MIXER
|
||||
name 'Tx2 Channels 5 MAP'
|
||||
value '1st adc sample'
|
||||
comment {
|
||||
access 'read write'
|
||||
type ENUMERATED
|
||||
count 1
|
||||
item.0 '1st adc sample'
|
||||
item.1 '2st adc sample'
|
||||
item.2 '3st adc sample'
|
||||
item.3 '4st adc sample'
|
||||
}
|
||||
}
|
||||
control.38 {
|
||||
iface MIXER
|
||||
name 'Tx2 Channels 6 MAP'
|
||||
value '1st adc sample'
|
||||
comment {
|
||||
access 'read write'
|
||||
type ENUMERATED
|
||||
count 1
|
||||
item.0 '1st adc sample'
|
||||
item.1 '2st adc sample'
|
||||
item.2 '3st adc sample'
|
||||
item.3 '4st adc sample'
|
||||
}
|
||||
}
|
||||
control.39 {
|
||||
iface MIXER
|
||||
name 'Tx2 Channels 7 MAP'
|
||||
value '1st adc sample'
|
||||
comment {
|
||||
access 'read write'
|
||||
type ENUMERATED
|
||||
count 1
|
||||
item.0 '1st adc sample'
|
||||
item.1 '2st adc sample'
|
||||
item.2 '3st adc sample'
|
||||
item.3 '4st adc sample'
|
||||
}
|
||||
}
|
||||
control.40 {
|
||||
iface MIXER
|
||||
name 'Tx2 Channels 8 MAP'
|
||||
value '1st adc sample'
|
||||
comment {
|
||||
access 'read write'
|
||||
type ENUMERATED
|
||||
count 1
|
||||
item.0 '1st adc sample'
|
||||
item.1 '2st adc sample'
|
||||
item.2 '3st adc sample'
|
||||
item.3 '4st adc sample'
|
||||
}
|
||||
}
|
||||
control.41 {
|
||||
iface MIXER
|
||||
name 'Tx2 Channels 9 MAP'
|
||||
value '1st adc sample'
|
||||
comment {
|
||||
access 'read write'
|
||||
type ENUMERATED
|
||||
count 1
|
||||
item.0 '1st adc sample'
|
||||
item.1 '2st adc sample'
|
||||
item.2 '3st adc sample'
|
||||
item.3 '4st adc sample'
|
||||
}
|
||||
}
|
||||
control.42 {
|
||||
iface MIXER
|
||||
name 'Tx2 Channels 10 MAP'
|
||||
value '1st adc sample'
|
||||
comment {
|
||||
access 'read write'
|
||||
type ENUMERATED
|
||||
count 1
|
||||
item.0 '1st adc sample'
|
||||
item.1 '2st adc sample'
|
||||
item.2 '3st adc sample'
|
||||
item.3 '4st adc sample'
|
||||
}
|
||||
}
|
||||
control.43 {
|
||||
iface MIXER
|
||||
name 'Tx2 Channels 11 MAP'
|
||||
value '1st adc sample'
|
||||
comment {
|
||||
access 'read write'
|
||||
type ENUMERATED
|
||||
count 1
|
||||
item.0 '1st adc sample'
|
||||
item.1 '2st adc sample'
|
||||
item.2 '3st adc sample'
|
||||
item.3 '4st adc sample'
|
||||
}
|
||||
}
|
||||
control.44 {
|
||||
iface MIXER
|
||||
name 'Tx2 Channels 12 MAP'
|
||||
value '1st adc sample'
|
||||
comment {
|
||||
access 'read write'
|
||||
type ENUMERATED
|
||||
count 1
|
||||
item.0 '1st adc sample'
|
||||
item.1 '2st adc sample'
|
||||
item.2 '3st adc sample'
|
||||
item.3 '4st adc sample'
|
||||
}
|
||||
}
|
||||
control.45 {
|
||||
iface MIXER
|
||||
name 'Tx2 Channels 13 MAP'
|
||||
value '1st adc sample'
|
||||
comment {
|
||||
access 'read write'
|
||||
type ENUMERATED
|
||||
count 1
|
||||
item.0 '1st adc sample'
|
||||
item.1 '2st adc sample'
|
||||
item.2 '3st adc sample'
|
||||
item.3 '4st adc sample'
|
||||
}
|
||||
}
|
||||
control.46 {
|
||||
iface MIXER
|
||||
name 'Tx2 Channels 14 MAP'
|
||||
value '1st adc sample'
|
||||
comment {
|
||||
access 'read write'
|
||||
type ENUMERATED
|
||||
count 1
|
||||
item.0 '1st adc sample'
|
||||
item.1 '2st adc sample'
|
||||
item.2 '3st adc sample'
|
||||
item.3 '4st adc sample'
|
||||
}
|
||||
}
|
||||
control.47 {
|
||||
iface MIXER
|
||||
name 'Tx2 Channels 15 MAP'
|
||||
value '1st adc sample'
|
||||
comment {
|
||||
access 'read write'
|
||||
type ENUMERATED
|
||||
count 1
|
||||
item.0 '1st adc sample'
|
||||
item.1 '2st adc sample'
|
||||
item.2 '3st adc sample'
|
||||
item.3 '4st adc sample'
|
||||
}
|
||||
}
|
||||
control.48 {
|
||||
iface MIXER
|
||||
name 'Tx2 Channels 16 MAP'
|
||||
value '1st adc sample'
|
||||
comment {
|
||||
access 'read write'
|
||||
type ENUMERATED
|
||||
count 1
|
||||
item.0 '1st adc sample'
|
||||
item.1 '2st adc sample'
|
||||
item.2 '3st adc sample'
|
||||
item.3 '4st adc sample'
|
||||
}
|
||||
}
|
||||
control.49 {
|
||||
iface MIXER
|
||||
name 'ADC4 Source'
|
||||
value 'Analog ADC4'
|
||||
comment {
|
||||
access 'read write'
|
||||
type ENUMERATED
|
||||
count 1
|
||||
item.0 'Analog ADC1'
|
||||
item.1 'Analog ADC2'
|
||||
item.2 'Analog ADC3'
|
||||
item.3 'Analog ADC4'
|
||||
}
|
||||
}
|
||||
control.50 {
|
||||
iface MIXER
|
||||
name 'ADC3 Source'
|
||||
value 'Analog ADC3'
|
||||
comment {
|
||||
access 'read write'
|
||||
type ENUMERATED
|
||||
count 1
|
||||
item.0 'Analog ADC1'
|
||||
item.1 'Analog ADC2'
|
||||
item.2 'Analog ADC3'
|
||||
item.3 'Analog ADC4'
|
||||
}
|
||||
}
|
||||
control.51 {
|
||||
iface MIXER
|
||||
name 'ADC2 Source'
|
||||
value 'Analog ADC2'
|
||||
comment {
|
||||
access 'read write'
|
||||
type ENUMERATED
|
||||
count 1
|
||||
item.0 'Analog ADC1'
|
||||
item.1 'Analog ADC2'
|
||||
item.2 'Analog ADC3'
|
||||
item.3 'Analog ADC4'
|
||||
}
|
||||
}
|
||||
control.52 {
|
||||
iface MIXER
|
||||
name 'ADC1 Source'
|
||||
value 'Analog ADC1'
|
||||
comment {
|
||||
access 'read write'
|
||||
type ENUMERATED
|
||||
count 1
|
||||
item.0 'Analog ADC1'
|
||||
item.1 'Analog ADC2'
|
||||
item.2 'Analog ADC3'
|
||||
item.3 'Analog ADC4'
|
||||
}
|
||||
}
|
||||
control.53 {
|
||||
iface MIXER
|
||||
name 'ADC1 Digital Mixer gc'
|
||||
value 'disable all'
|
||||
comment {
|
||||
access 'read write'
|
||||
type ENUMERATED
|
||||
count 1
|
||||
item.0 'disable all'
|
||||
item.1 'ADC1 data'
|
||||
item.2 'ADC2 data'
|
||||
item.3 'ADC3 data'
|
||||
item.4 'ADC4 data'
|
||||
}
|
||||
}
|
||||
control.54 {
|
||||
iface MIXER
|
||||
name 'ADC1 Digital Mixer src'
|
||||
value 'ADC1 data'
|
||||
comment {
|
||||
access 'read write'
|
||||
type ENUMERATED
|
||||
count 1
|
||||
item.0 'disable all'
|
||||
item.1 'ADC1 data'
|
||||
item.2 'ADC2 data'
|
||||
item.3 'ADC3 data'
|
||||
item.4 'ADC4 data'
|
||||
}
|
||||
}
|
||||
control.55 {
|
||||
iface MIXER
|
||||
name 'ADC2 Digital Mixer gc'
|
||||
value 'disable all'
|
||||
comment {
|
||||
access 'read write'
|
||||
type ENUMERATED
|
||||
count 1
|
||||
item.0 'disable all'
|
||||
item.1 'ADC1 data'
|
||||
item.2 'ADC2 data'
|
||||
item.3 'ADC3 data'
|
||||
item.4 'ADC4 data'
|
||||
}
|
||||
}
|
||||
control.56 {
|
||||
iface MIXER
|
||||
name 'ADC2 Digital Mixer src'
|
||||
value 'ADC2 data'
|
||||
comment {
|
||||
access 'read write'
|
||||
type ENUMERATED
|
||||
count 1
|
||||
item.0 'disable all'
|
||||
item.1 'ADC1 data'
|
||||
item.2 'ADC2 data'
|
||||
item.3 'ADC3 data'
|
||||
item.4 'ADC4 data'
|
||||
}
|
||||
}
|
||||
control.57 {
|
||||
iface MIXER
|
||||
name 'ADC3 Digital Mixer gc'
|
||||
value 'disable all'
|
||||
comment {
|
||||
access 'read write'
|
||||
type ENUMERATED
|
||||
count 1
|
||||
item.0 'disable all'
|
||||
item.1 'ADC1 data'
|
||||
item.2 'ADC2 data'
|
||||
item.3 'ADC3 data'
|
||||
item.4 'ADC4 data'
|
||||
}
|
||||
}
|
||||
control.58 {
|
||||
iface MIXER
|
||||
name 'ADC3 Digital Mixer src'
|
||||
value 'ADC3 data'
|
||||
comment {
|
||||
access 'read write'
|
||||
type ENUMERATED
|
||||
count 1
|
||||
item.0 'disable all'
|
||||
item.1 'ADC1 data'
|
||||
item.2 'ADC2 data'
|
||||
item.3 'ADC3 data'
|
||||
item.4 'ADC4 data'
|
||||
}
|
||||
}
|
||||
control.59 {
|
||||
iface MIXER
|
||||
name 'ADC4 Digital Mixer gc'
|
||||
value 'disable all'
|
||||
comment {
|
||||
access 'read write'
|
||||
type ENUMERATED
|
||||
count 1
|
||||
item.0 'disable all'
|
||||
item.1 'ADC1 data'
|
||||
item.2 'ADC2 data'
|
||||
item.3 'ADC3 data'
|
||||
item.4 'ADC4 data'
|
||||
}
|
||||
}
|
||||
control.60 {
|
||||
iface MIXER
|
||||
name 'ADC4 Digital Mixer src'
|
||||
value 'ADC4 data'
|
||||
comment {
|
||||
access 'read write'
|
||||
type ENUMERATED
|
||||
count 1
|
||||
item.0 'disable all'
|
||||
item.1 'ADC1 data'
|
||||
item.2 'ADC2 data'
|
||||
item.3 'ADC3 data'
|
||||
item.4 'ADC4 data'
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -2,6 +2,7 @@
|
|||
|
||||
dtc -@ -I dts -O dtb -o seeed-2mic-voicecard.dtbo seeed-2mic-voicecard-overlay.dts
|
||||
dtc -@ -I dts -O dtb -o seeed-4mic-voicecard.dtbo seeed-4mic-voicecard-overlay.dts
|
||||
dtc -@ -I dts -O dtb -o seeed-8mic-voicecard.dtbo seeed-8mic-voicecard-overlay.dts
|
||||
|
||||
# cp *.dtbo /boot/overlays
|
||||
# dtoverlay seeed-2mic-voicecard
|
||||
|
|
|
|||
80
seeed-8mic-voicecard-overlay.dts
Normal file
80
seeed-8mic-voicecard-overlay.dts
Normal file
|
|
@ -0,0 +1,80 @@
|
|||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
/ {
|
||||
compatible = "brcm,bcm2708";
|
||||
|
||||
fragment@0 {
|
||||
target = <&i2s>;
|
||||
__overlay__ {
|
||||
#sound-dai-cells = <0>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
fragment@1 {
|
||||
target-path = "/clocks";
|
||||
__overlay__ {
|
||||
ac108_mclk: codec-mclk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
fragment@2 {
|
||||
target = <&i2c1>;
|
||||
__overlay__ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "okay";
|
||||
|
||||
ac108_a: ac108@35{
|
||||
compatible = "x-power,ac108_0";
|
||||
reg = <0x35>;
|
||||
#sound-dai-cells = <0>;
|
||||
data-protocol = <0>;
|
||||
};
|
||||
|
||||
ac108_b: ac108@3b{
|
||||
compatible = "x-power,ac108_1";
|
||||
reg = <0x3b>;
|
||||
#sound-dai-cells = <0>;
|
||||
data-protocol = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
fragment@3 {
|
||||
target = <&sound>;
|
||||
|
||||
sound_overlay: __overlay__ {
|
||||
compatible = "simple-audio-card";
|
||||
simple-audio-card,format = "dsp_a";
|
||||
simple-audio-card,name = "seeed-8mic-voicecard";
|
||||
status = "okay";
|
||||
|
||||
simple-audio-card,bitclock-master = <&codec_dai>;
|
||||
simple-audio-card,frame-master = <&codec_dai>;
|
||||
|
||||
cpu_dai: simple-audio-card,cpu {
|
||||
sound-dai = <&i2s>;
|
||||
dai-tdm-slot-num = <2>;
|
||||
dai-tdm-slot-width = <32>;
|
||||
dai-tdm-slot-tx-mask = <1 1 0 0>;
|
||||
dai-tdm-slot-rx-mask = <1 1 0 0>;
|
||||
};
|
||||
codec_dai: simple-audio-card,codec {
|
||||
sound-dai = <&ac108_b>;
|
||||
clocks = <&ac108_mclk>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
__overrides__ {
|
||||
card-name = <&sound_overlay>,"seeed-voicecard,name";
|
||||
};
|
||||
};
|
||||
|
||||
BIN
seeed-8mic-voicecard.dtbo
Normal file
BIN
seeed-8mic-voicecard.dtbo
Normal file
Binary file not shown.
|
|
@ -125,10 +125,10 @@ static int asoc_simple_card_startup(struct snd_pcm_substream *substream)
|
|||
if (ret)
|
||||
clk_disable_unprepare(dai_props->cpu_dai.clk);
|
||||
|
||||
rtd->cpu_dai->driver->playback.channels_min = 4;
|
||||
rtd->cpu_dai->driver->playback.channels_max = 4;
|
||||
rtd->cpu_dai->driver->capture.channels_min = 4;
|
||||
rtd->cpu_dai->driver->capture.channels_max = 4;
|
||||
rtd->cpu_dai->driver->playback.channels_min = 8;
|
||||
rtd->cpu_dai->driver->playback.channels_max = 8;
|
||||
rtd->cpu_dai->driver->capture.channels_min = 8;
|
||||
rtd->cpu_dai->driver->capture.channels_max = 8;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in a new issue